Kaiser,
I’m curious about the coordinating of the two SM’s. Are they both producing a GPIO output that the FPGA is using to coordinate the signal generation? Do you monitor the two GPIO outputs continuously? Does the bug follow e.g. SM #2 trigger arriving before SM #1? Or SM #2 getting a full sweep ahead or behind SM #1?
Our sweeps are not deterministic, so I can certainly see some variance in timing between the two SM’s playing a role in this.
If you could use something like I/Q streaming, and have the FPGA generate the trigger, or have SM #1 sweeping and generating the trigger and SM #2 streaming at one of the frequencies with a trigger input, something like this might be more solid. Just my thoughts…